1. Field of the Invention
This invention relates to solid state imagers and in particular to the readout of image information from charge transfer device arrays.
2. Description of the Prior Art
One of the most useful solid state image sensors is the CID (charge injection device) array. Such an array comprises a matrix of CID storage sites in which signal charges are collected in proportion to the intensity of incident radiation forming an image focused onto the array. The CID array has good antiblooming capabilities, is immune from image burn and has a higher modulation transfer function than other charge transfer devices, such as CCDs. Despite these advantages, however, difficulties have been experienced in accurately reading the magnitudes of the charges collected at the discrete sites of CID arrays fabricated from certain semiconductor materials.
These difficulties can be best understood by referring to FIG. 1 which schematically illustrates a conventional CID array. The array 1 comprises a substrate of semiconductor material of one conductivity type supporting a layer of insulator material on which are formed a multiplicity of conductive pads. The array is geometrically divided into a plurality of charge storage sites, such as that indicated at 2, for collection of radiation-generated minority carriers. Each of the sites includes a pair of the pads, designated a row pad 3 and a column pad 4, and each pad defines a CIS (conductor, insulator, semiconductor) capacitive cell comprising the pad itself and the underlying portions of the insulating and semiconductor layers. The charge storage capacity of each cell is determined by the size of a potential well formed in the semiconductor layer thereof by a potential established on the cell pad. The two pads at each site are closely coupled, as is known in the art, to enable charge to be transferred between the capacitive cells in the site. The row pads in each row are electrically connected to a respective row line 5. Similarly, the column pads in each column are electrically connected to a respective column line 6.
In the prior art, readout of the array is typically accomplished by apparatus for sequentially selecting the individual sites and applying voltages of predetermined magnitudes to the row and column lines connected thereto. The magnitudes of these voltages are chosen such that they change the sizes of the potential wells in the row and column cells of the selected site in a manner which effects transfer of the signal charge out of one or both of the cells. The magnitude of the transferred signal charge is then sensed by detecting changes in potential on either the row or the column line and producing a signal voltage representing the magnitude of the charge transferred. One such prior art read-out apparatus is described in U.S. Pat. No. 3,935,446 to Gerald J. Michon which is assigned to the assignee of the present invention and is incorporated herein by reference.
Such prior art circuitry has been effective for determining the magnitudes of charges collected in the individual sites of arrays fabricated from semiconductor materials having high charge transfer efficiencies, such as silicon, but it has not been effective for determining the magnitudes of charges collected in arrays fabricated from materials having lower charge transfer efficiencies, such as indium antimonide. It is desirable to utilize arrays fabricated from these latter materials because they are particularly suitable for detecting radiation in the infrared portion of the spectrum.
One of the reasons for the above-described ineffectiveness of prior art readout circuitry can be understood by considering the effect, at unselected sites, of the application of the predetermined voltages to the row and column lines of a selected site. When these voltages are applied to a selected row line m and a selected column line n, the size of the potential wells is changed not only in the row and column cells of the selected site at the coordinate m, n, but also in all other row cells in row m and in all other column cells in column n. This change in size of the potential wells at non-selected sites causes charge transfers between the row and column cells at these sites which are unnecessary for sensing the signal charge at the selected site. In semiconductor materials with low charge transfer efficiencies these charge transfers are often imperfect and thus the charge transferred between cells is not precisely the magnitude expected. In such case, a spurious signal representative of the cumulative errors in the magnitudes of the charges transferred at the unselected sites connected to the selected row and column line is developed on each of these lines. Of particular interest is the spurious signal developed on the line utilized to produce the signal voltage representative of the signal charge transferred at the selected site. The magnitude of this signal is significant with respect to the magnitude of the signal voltage developed on the line and causes a substantial error in the measurement of the signal charge at the selected site. It is desirable to prevent the production of such spurious signals on the lines utilized to produce the signal voltages.
A prior art readout circuit which accomplishes this objective in arrays having high charge transfer efficiencies is illustrated schematically in FIG. 2. This circuit accomplishes the objective by producing each signal voltage on the selected column line while avoiding charge transfers in all sites connected to this column line, except that in the selected row. During operation of the circuit, a potential V.sub.R is continually applied to all pads in the array. This potential establishes equal charge storage capacities in the row and column cells of each site as is illustrated by the potential well diagram of FIG. 3A. At each site there are a bias charge of magnitude Q.sub.B and a signal charge of magnitude Q.sub.S which are equally shared by the row and column cells. The bias charge in each site is the maximum charge that can be stored in a column cell when the potential V.sub.R is applied to the column pad thereof. The signal charge in each site is the charge collected at the site between readings.
As is shown in a timing diagram included in FIG. 2, reading of the array is begun by applying a row injection pulse to a transistor switch connecting row line 1 to ground potential. This essentially collapses the potential well in the row cells of row 1 (to about 0.1 volt in silicon) and causes charge to be transferred into the respective column cells until they are filled to capacity (FIG. 3B). Because each column cell is capable of holding the bias charge only, the signal charge in each site of row 1 is injected into the substrate.
After the row injection pulse terminates, the potential V.sub.R is re-established in row line 1, re-establishing the charge storage capacities existing in the row cells prior to injection and causing the bias charges to again be equally shared by the row and column cells at each site (FIG. 3C). The absence of signal charge at each site in row 1 causes the voltages on the respective column pads to differ from the potential V.sub.R previously established thereon by a potential difference proportional to the magnitude of the signal charge injected therefrom. These potential differences are measured by sequentially applying column read pulses to transistor switches connecting the individual column lines to one side of a resistor R having the opposite side referenced to the potential V.sub.R. As each column line is thus connected, current having an amplitude proportional to the respective potential difference passes through R causing the potential V.sub.R to be re-established on the column line (FIG. 3D). This current amplitude is sensed by an amplifier A which produces a signal voltage e.sub.o representative of the magnitude of the signal charge injected at the respective site in row 1.
After the signal charges injected at the row 1 sites have been sensed, the signal charges in the remaining rows are sequentially injected and sensed in similar fashion. Because this manner of reading the array causes charge transfers only in the row of sites being read, and thus causes no spurious signals on the column lines, the circuit of FIG. 2 would seem useful for reading arrays having low charge transfer efficiencies as well as those having high charge transfer efficiencies. Such is not the case, however. It has been found that the collapsing of potential wells to sense signal charges in a selected row of sites, as is depicted in FIG. 3B, causes production of spurious signal by the selected row itself. This results because all charge cannot be readily transferred out of cells in semiconductor materials of low charge transfer efficiency and charge erroneously remaining in the cell with the collapsed potential well causes a corresponding error in the measurement of the charge injected at the site.
Another problem, experienced with CID array readout circuitry in general, is thermal (KT/C) noise produced within the impedances of transistor switches utilized to make connections with the column or row lines on which the signal voltages are produced. For a discussion of the cause and the magnitude of thermal noise refer to M. Schwartz; Information Transmission, Modulation and Noise; pages 213-215 (1959). The instantaneous amplitude of this noise at the time each switch is opened causes an unpredictable offset in a DC reference voltage established on the line connected to the switch and this offset causes a corresponding error in the signal voltage later produced. A correlated double sampling technique useful for eliminating thermal noise is described by D. Barbe in Imaging Devices Using the Charge-Coupled Concept, Proceedings of the IEEE, Vol. 63, No. 1, pages 46-49 (January 1975). Use of this technique requires that the actual voltage on each line be sampled after opening of the switch connected thereto and again at the time the signal voltage is produced. Such double sampling is not feasible in prior art circuitry such as that illustrated in FIG. 2, because the amplifier used to sense the signal voltage on each line is sequentially switched from line to line after the signal voltages are produced.